Advancing Hardware Implementation of Hyperdimensional Computing for Edge Intelligence
| dc.contributor.author | Hassan, Eman | |
| dc.contributor.author | Bettayeb, Meriem | |
| dc.contributor.author | Mohammad, Baker | |
| dc.date.accessioned | 2024-10-28T07:27:37Z | |
| dc.date.available | 2024-10-28T07:27:37Z | |
| dc.date.issued | 2024-04-22 | |
| dc.description.abstract | Hyperdimensional Computing (HDC) is a promising paradigm known for its energy efficiency and simplicity. Human brain functions inspire HDC, which operates in high-dimensional spaces with low-precision data, making it suitable for efficient machine-learning applications. This paper analyzes the State-of-the-Art (SOTA) significance and challenges of implementing HDC on diverse hardware platforms, including Application Specific Integrated Circuits (ASIC), Central Processing Units (CPU), and Field-Programmable Gate Arrays (FPGA), and explores its potential in In-Memory Computing (IMC). Also, the significance of hardware-accelerated Associative Memory (AM) in HDC systems is discussed, emphasizing its role in optimizing overall performance and efficiency. Keywords: Associative Memory, Encoders, Hardware Implementation, Hyperdimensional Computing | |
| dc.identifier.citation | Hassan, E., Bettayeb, M., & Mohammad, B. (2024, April). Advancing hardware implementation of hyperdimensional computing for edge intelligence. In 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS) (pp. 169-173). IEEE. | |
| dc.identifier.doi | https://doi.org/10.1109/AICAS59952.2024.10595942 | |
| dc.identifier.uri | https://repository.adu.ac.ae/handle/1/6869 | |
| dc.language.iso | en | |
| dc.publisher | IEEE Xplore | |
| dc.title | Advancing Hardware Implementation of Hyperdimensional Computing for Edge Intelligence | |
| dc.type | Conference Paper |