Advancing Hardware Implementation of Hyperdimensional Computing for Edge Intelligence

Abstract

Hyperdimensional Computing (HDC) is a promising paradigm known for its energy efficiency and simplicity. Human brain functions inspire HDC, which operates in high-dimensional spaces with low-precision data, making it suitable for efficient machine-learning applications. This paper analyzes the State-of-the-Art (SOTA) significance and challenges of implementing HDC on diverse hardware platforms, including Application Specific Integrated Circuits (ASIC), Central Processing Units (CPU), and Field-Programmable Gate Arrays (FPGA), and explores its potential in In-Memory Computing (IMC). Also, the significance of hardware-accelerated Associative Memory (AM) in HDC systems is discussed, emphasizing its role in optimizing overall performance and efficiency.

Keywords: Associative Memory, Encoders, Hardware Implementation, Hyperdimensional Computing