A Scalable and Integrated Reconfigurable Intelligent Surface

Abstract

A scalable reconfigurable intelligent surface (RIS) architecture with both centralized and distributed control capability is presented. The RIS is implemented using a one-bit phase reconfigurable unit cell (UC) designed for X-band operation. The UC is realized by embedding a PIN diode into a slotted copper patch, achieving a maximum phase shift at 9.5 GHz with a phase difference of (Formula presented.) across the 9–10 GHz band. The proposed RIS enables real-time reconfiguration, with each element controlled through an FPGA achieving an update time below 0.1 ms. In addition, multiple control interfaces are supported, including LAN, USB, and WiFi. The measurement results of a (Formula presented.) single RIS tile prototype validate beam steering from (Formula presented.) to (Formula presented.) and gain performance, demonstrating a peak gain of 20.2 dBi at broadside (Formula presented.) and 18.2 dBi at (Formula presented.). To demonstrate scalability, a four-tile prototype of (Formula presented.) (each tile consisting of (Formula presented.) UCs) is fabricated. Each tile can be independently programmed via its dedicated interface, or alternatively, a single interface module (WiFi, LAN, or USB) can distribute ON/OFF configurations across all tiles, thereby enabling flexible and scalable control of the RIS.

Keywords: beam steering, metasurface, reconfigurable intelligent surfaces, scalable, Closed loop control systems, Distributed parameter control systems, Interlocking signals, Reconfigurable architectures.