Network-on-Chip based MPSoC architecture for k-mean clustering algorithm

Abstract

Data and image segmentation plays pivotal role in the application of machine learning. k-means, as a tool for unsupervised clustering, is a widely used algorithm for segmentation due to its inherent simplicity and efficiency. k-means partitions datasets into subsets based on their fitness value. As such k-means is a well suited algorithm for implementation on hardware platform such as Field Programmable Gate Array (FPGA) but requires high computation time. Hardware accelerators can help in reducing the computation complexity of the algorithm. In this paper, we present a simplified multicore based scalable hardware architecture for implementation of k-means. Mean and fitness modules in proposed architecture are further unfolded to further enhance the speed of k-means clustering algorithm. The unfolding factor has to be selected by keeping the area of the target device in check. In the proposed architecture, the cores are further connected through Network on Chip (NoC) interconnect network which allows for higher scalability while elevating the bottleneck of message passing. The performance of our MPSoC architecture has been evaluated with respect to Average Speedup, Average Throughput and Area consumption with and without use of NoC interconnect. Finally, we compare the use of different NoC interconnect models with respect to maximum Operating Frequency, average Throughput and Area overhead.

Keywords Machine learning, FPGA, Network on Chip (NoC)