Prioritized direction based switch for bufferless network on chip architecture

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dc.contributor.authorKhawaja, Sajid Gul
dc.contributor.authorMushtaq, Mian Hamza
dc.contributor.authorKhan, Shoab A
dc.date.accessioned2024-11-18T07:15:36Z
dc.date.available2024-11-18T07:15:36Z
dc.date.issued2011
dc.description.abstractThis paper represents a bufferless Network on Chip (NoC) architecture for a generic multi-array based architecture. A weighted priority based routing technique will be employed that handles contention based on destination direction. The results will represent the comparative effectiveness of the design with a XY based switch. Matrix multiplication application is tested and mapped as the process entities (PEs) to demonstrate the effectiveness of the NoC design. The NoC architecture is synthesized and tested on FPGA platform as a prototype. Keywords Bufferless, Routing Scheme, NoC, SoC
dc.identifier.citationKhawaja, S. G., Mushtaq, M. H., & Khan, S. A. (2011). Prioritized direction based switch for bufferless network on chip architecture. International Journal of Electrical and Computer Sciences, 11(4), 14-18.
dc.identifier.issn115704-8383
dc.identifier.urihttps://repository.adu.ac.ae/handle/1/7052
dc.language.isoen_US
dc.publisherAcademia
dc.titlePrioritized direction based switch for bufferless network on chip architecture
dc.typeArticle

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